1. Field of the Invention
The present invention relates to an optical disc device which can read binary data, which will be referred to as header data, in a header area on a optical disc, such as a mini disc or MD or a compact disc-recordable or CD-R, in which a sector address or the like is pre-recorded, using light, and then write the data on a recording area of the optical disc. More particularly, the present invention relates to an optical disc device which can generate a clock in synchronism with binary channel data recorded between two adjacent header areas on an optical disc and then read the channel data at a high speed.
2. Description of the Prior Art
Referring now to FIG. 7, there is illustrated a block diagram showing the structure of a prior art optical disc device. In the figure, reference numeral 1 denotes a channel phase-locked loop or channel PLL which can generate a read clock signal RCK from channel data D1, which is channel data or a header data read out of an optical disc (not shown) such as an MD or CD-R; and 2 denotes a wobble phase-locked loop or wobble PLL, which can generate a write clock signal WCK from a wobble signal S1 detected from a wobbly groove in each track wobbling at predetermined intervals, which is formed on the optical disc.
Reference numeral 5 denotes a phase comparator which can compare the phase of the channel data D1 with that of the read clock signal RCK and then furnish a phase error signal representing the phase displacement between the channel data D1 and the read clock signal RCK; 6 denotes a frequency comparator which can compare the frequency of the channel data D1 with that of the read clock signal RCK and then furnish a frequency error signal representing the frequency displacement between the channel data D1 and the read clock signal RCK; 7 denotes a charge pump which can increase the voltage of the phase error signal from the phase comparator 5 to a predetermined voltage so as to convert the phase error signal into a first current having an amplitude corresponding to the phase displacement between the channel data D1 and the read clock signal RCK; and 8 denotes another charge pump which can increase the voltage of the frequency error signal from the frequency comparator 6 to a predetermined voltage so as to convert the frequency error signal into a second current having an amplitude corresponding to the frequency displacement between the channel data D1 and the read clock signal RCK.
Reference numeral 9 denotes an adder which can obtain the sum of the first current representing the phase displacement from the charge pump 7 and the second current representing the frequency displacement from the charge pump 8; 10 denotes a low-pass filter which can generate an error voltage and furnish the error voltage as a control voltage by attenuating unnecessary high-frequency components of the summation result or the summation error signal furnished by the adder 9; and 11 denotes a voltage controlled oscillator or VCO which can generate a read clock signal RCK having a frequency corresponding to the control voltage furnished by the low-pass filter 10.
Reference numeral 15 denotes a frequency comparator which can compare the frequency of the wobble signal S1 with that of the output signal of a 1/186 frequency divider 19 and then furnish a frequency error signal representing the frequency displacement between the wobble signal S1 and the output signal from the frequency divisor 19; and 16 denotes a charge pump which can increase the voltage of the frequency error signal from the frequency comparator 15 to a predetermined voltage so as to convert the frequency error signal into a current having an amplitude corresponding to the frequency displacement between the wobble signal S1 and the output signal of the frequency divisor 19.
Reference numeral 17 denotes a low-pass filter which can generate an error voltage and then furnish the error voltage as a control voltage by attenuating unnecessary high-frequency components of the frequency error signal furnished by the charge pump 16; and 18 denotes a voltage controlled oscillator which can generate a write clock signal WCK having a frequency corresponding to the control voltage furnished by the low-pass filter 17. The 1/186 frequency divider 19 divides the frequency of the write clock signal WCK furnished by the voltage controlled oscillator 18 by a given number 186 so as to generate and furnish a feedback signal having the same frequency as the wobble signal S1 to the frequency comparator 15.
In operation, the optical disc device reads channel data from an optical disc and then writes the channel data in a recording area on the optical disc. Since header data pre-recorded and channel data written into a recording area on an optical disc was recorded by different recording devices, respectively, header data and channel data which can be read out from an optical disc upon reproduction of the channel data are discrete and are out of phase with respect to each other.
When reproducing data recorded on an optical disc, it is necessary to quickly generate a clock signal in synchronism with header and channel data which are discrete and are out of phase with respect to each other, and furnish the clock signal to a signal processing circuit located at the next stage. When the optical disc device handles a not-yet-recorded area where no data is pre-recorded, a synchronous clock signal generated can become a free-running state, resulting in an off-track error. As a result, the frequency of the clock signal will be displaced with respect to a header data which is to be processed next, and therefore it takes a long time to generate a synchronous clock signal for reading the next header data and a channel data in a recording area located behind the header data.
FIG. 8 shows the wave form of the control voltage applied to the VCO 11 when the optical disc device handles a not-yet-recorded area 25. In order to prevent a large displacement of the frequency of the clock signal, the output of the channel PLL 1 can be repeatedly held in synchronism with a plurality of data in header areas 26, 27, 28, and 29 which are intermittently applied to the channel PLL 1, while the optical disc device handles the not-yet-recorded area 25 as shown in FIG. 8, for example.
The frequency of the read lock signal RCK can be controlled to reproduce data properly in the following manner. In FIG. 8, it is assumed that at time t0 the control voltage has an initial value V0 which differs from a locked voltage V1. If the control voltage reaches the locked voltage V1, the channel PLL 1 can be locked so as to furnish a read clock signal RCK having a frequency suitable for reproducing data properly.
When a control operation on the channel PLL 1 is started at time t0 in order to increase the control voltage having the initial value V0 to the locked voltage V1, data stored in the first header area 26 is applied as the channel data D1 to the phase and frequency comparators 5 and 6 of the channel PLL 1. The phase comparator 5 then compares the phase of the channel data D1 with that of the read clock signal RCK which is being furnished by the channel PLL 1 at that time. The phase comparator 5 furnishes a phase error signal representing the phase displacement between the channel data D1 and the read clock signal RCK to the charge pump 7. Simultaneously, the frequency comparator 6 compares the frequency of the channel data D1 with that of the read clock signal RCK. The frequency comparator 6 then furnishes a frequency error signal representing the frequency displacement between the channel data D1 and the read clock signal RCK to the charge pump 8. The charge pump 7 increases the voltage of the phase error signal from the phase comparator 5 to a predetermined voltage so as to convert the phase error signal into a current having an amplitude corresponding to the phase displacement between the channel data D1 and the read clock signal RCK and then deliver the current to the adder 9. The charge pump 8 increases the voltage of the frequency error signal from the frequency comparator 6 to a predetermined voltage so as to convert the frequency error 6 signal into a current having an amplitude corresponding to the frequency displacement between the channel data D1 and the read clock signal RCK and then deliver the current to the adder 9. The adder 9 obtains the sum of both the currents from the charge pumps 7 and 8 and then delivers to the summation result to the low-pass filter 10 as the summation error signal. The low-pass filter 10 generates an error voltage as a control signal to the VCO 11 by attenuating unnecessary high-frequency components of the summation error signal from the adder 9. The VCO 11 then generates a read clock signal RCK having a frequency corresponding to the control voltage from the low-pass filter 10. The read clock signal RCK is also fed back into both the phase and frequency comparators 5 and 6 as a feedback signal.
In the feedback loop, while data recorded in the header area 26 shown in FIG. 8 is input to the channel PLL 1 as the data D1, the control voltage applied to the VCO 11 increases as indicated by reference numeral 31 in FIG. 8. Furthermore, when the optical disc device passes through the header area 26 and then reaches an area between the header areas 26 and 27 where no data is recorded, the channel PLL 1 leaves the control voltage unchanged so that the control voltage has a value V01 that it reached at the time just before the optical disc device has passed through the header area 26, and therefore the channel PLL 1 becomes a holding state in which it maintains its output. The read clock signal RCK consequently has a phase and a frequency corresponding to the control voltage V01 which is locked as mentioned above.
After that, the control voltage increases similarly when the optical disc device reaches the next header area 27, and the control voltage is held at a voltage of V02 just after the optical disc device has passed through the header area 27. Furthermore, the control voltage increases similarly when the optical disc device reaches the next header area 28, and the control voltage is held at a locked voltage of V1 just after the optical disc device has passed through the header area 28. As a result, the read clock signal RCK has a phase and a frequency corresponding to the control voltage held at the locked voltage V1. The optical disc device thus can start to read data recorded in the header area 29 at time t2 when the optical disc device reaches the header area 29, and start to reproduce data recorded in a data recording area 32 located just behind the header area 29 at time t3 when the optical disc device reaches the recording area 32.
On the other hand, the wobble PLL 2, which is disposed separately from the channel PLL 1, can generate a write clock signal WCK having the same phase and frequency as the read clock signal RCK by multiplying the frequency of the wobble signal S1 applied to the wobble PLL 2. The frequency comparator 15 compares the frequency of the wobble signal SI with that of the feedback signal, i.e., the output signal of the 1/186 frequency divider 19. The frequency comparator 15 then furnishes a frequency error signal representing the frequency displacement between the wobble signal S1 and the output signal of the 1/186 frequency divider 19 to the charge pump 16. The charge pump 16 increases the voltage of the frequency error signal from the frequency comparator 15 to a predetermined voltage so as to convert the frequency error signal into a current having an amplitude corresponding to the frequency displacement between the wobble signal S1 and the output signal of the 1/186 frequency divider 19 and then deliver the current to the low-pass filter 17. The low-pass filter 17 generates an error voltage and furnishes the error voltage as a control voltage to the VCO 18 by attenuating unnecessary high-frequency components of the frequency error signal furnished by the charge pump 16. The VCO 18 then generates a write clock signal WCK having a frequency corresponding to the control voltage from the low-pass filter 17. The write clock signal WCK is also fed back as the feedback signal into the frequency comparator 16 after the frequency of the write clock signal WCK is divided by the 1/186 frequency divider 19 by 186 so that the feedback signal into the frequency comparator 15 has the same frequency as the wobble signal S1.
Such a prior art optical disc device which is so constructed has a few disadvantages. The first disadvantage is that since a control operation is performed on the channel PLL 1 only if data read out of each header area is intermittently applied to the channel PLL 1 when the optical disc device handles a not-yet-recorded area on an optical disc, it takes a long time to bring the optical disc device to a state in which it can read header data or channel data by locking the channel PLL 1.
In order to cause the channel PLL 1 to lock itself for header data in a not-yet-recorded area as soon as possible, the frequency of the output of the VCO of the channel PLL 1 that can be controlled has to be limited in a narrow range of adjustment. A second disadvantage is thus that if the frequency range of adjustment is limited, the access time is delayed for an optical disc which can rotate at only a rpm that can be locked and in which data are pre-recorded by means of a servo having a constant linear velocity (CLV), such as a CD-ROM, or a DVD-ROM.